library verilog;
use verilog.vl_types.all;
entity lab2_fre_div3_021 is
    port(
        B2_027          : out    vl_logic;
        S               : in     vl_logic_vector(1 downto 0);
        C_027           : in     vl_logic;
        D_027           : in     vl_logic
    );
end lab2_fre_div3_021;
